The present invention relates to an integrated circuit including an input protection circuit cell.
FIG. 1 shows an input protection circuit cell 70 and a power supply cell 71 according to a conventional technology. To ensure ESD robustness, the input protection circuit cell 70 according to a conventional technology uses diodes 1 and 2. The diodes each have a capacitance of several picofarads and are reversely coupled between a power supply voltage (VDD) and a signal input line and between the signal input line and a ground (GND). A series resistor 40 is serially coupled to the signal input line. In a power supply cell 51, as shown in FIG. 1, an input circuit 43 and a clamp circuit 4 are parallel coupled between VDD and GND.
FIG. 2 shows in more detail the inside of the input circuit 43 and the clamp circuit 4 according to the conventional technology. A diode 44 is coupled between input and output sides of the input circuit 43. The clamp circuit 4 includes a resistor 11 and a capacitor 12 that are serially coupled between VDD and GND. The clamp circuit 4 also includes an NMOS transistor 10 that uses the source terminal for the power supply voltage and the drain terminal for the ground. The clamp circuit 4 further includes an inverter 13 that has an input section coupled to a node between the resistor 11 and the capacitor 12 and an output section coupled to the gate terminal of the NMOS transistor 10.
FIG. 3 shows an example layout of the input protection circuit cell 70 and the power supply cell 71.
FIG. 4 shows a chip layout of an integrated circuit 80 mounted with an input protection circuit cell and a power supply cell according to a conventional technology. As shown in FIG. 4, the layout is configured to include input protection circuit cells 50 and 51 and power supply cells 26 and 29. The input protection circuit cells 50 and 51 each are equivalent to the input protection circuit cell 70. The power supply cells 26 and 29 each are equivalent to the power supply cell 71. The power supply cells 26 and 29 include clamp circuits 26a and 29a. In the overall chip configuration, as shown in FIG. 4, the input protection circuit cells 50 and 51 are located adjacently to an RF input pad. The power supply cells 26 and 29 including the clamp circuit 4 are located adjacent to a VDD pad 20 or a GND pad 25.
Patent Documents 1 and 2 describe the methods of decreasing parasitic capacitance in an ESD protection circuit.
Patent Document 1: Japanese Unexamined Patent Publication No. 2007-311813
Patent Document 2: Japanese Unexamined Patent Publication No.